The present disclosure relates to semiconductor device fabrication, for example, six-transistor static random access memory (6T SRAM) bitcells. The present disclosure relates more specifically to active contact-gate contact interconnects for mitigating adjacent gate electrode shortages.
As the dimensions of transistor devices continue to shrink, various issues arise imposing increasing demands for fabrication of more condensed components. For example, smaller transistors allow more transistors to be placed on a single substrate and thereby allow relatively large circuit systems to be incorporated on a single, relatively small die area. However, smaller transistors also require reduced feature sizes and overall device scaling. Aggressive scaling of, e.g., a six transistor static random access memory (6T SRAM) bitcells, can be difficult to implement since the scaling generally causes a decrease in contacted polysilicon pitch (CPP) distance between gate electrodes. Use of current contact interconnect formation techniques, e.g. gate-active contact overlap, generally results in higher risk of shortages of adjacent gate electrodes and thus functional loss of the device. Additionally, use of current contact interconnect layouts including contacts of varying shapes and sizes may result in parametric yield loss of the device.